A memory device such as a dynamic random access memory (DRAM) device conventionally comprises a number of memory cells arranged in rows and columns. The memory cells are grouped into sub-arrays. Each memory cell includes a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The access transistors of the memory cells connect to internal signal lines, referred to as bit or digit lines. The digit lines connect to input/output lines through input/output transistors, which are used as switching devices to allow data to be transmitted between the digit lines and the input/output lines during a read or write mode.
A number of sense amplifiers are included in the memories to both sense data stored in the memory cells and amplify the data for outputting. Each sense amplifier compares a charge stored on a memory cell with a known reference. A sense amplifier conventionally connects to two digit lines to perform the sensing operation. In the sensing operation, the two digit lines are first equalized using an equilibrate circuit to a reference voltage which is typically, but not limited to, one half of the supply voltage (Vcc) also sometimes referred to as DVC2. After that, the digit lines are driven to opposite voltage levels. That is, one of the digit lines is driven to Vcc and the other is driven to ground. The voltage on the digit line connected to the memory cell being accessed indicates the value of data stored in the memory cell.
In an open digit line memory device, all digit lines are interleaved. Specifically, due to the relatively larger dimensions of a sense amplifier compared with the dimensions of a memory cell, one digit line of a sub-array connects to one sense amplifier on one side of the sub-array, and an adjacent digit line connects to another sense amplifier on the other side of the sub-array. Therefore, a digit line has a terminated end that directly couples to the sense amplifier through which the logic states are programmed or sensed and an extended or unterminated end that has the highest impedance path to that sense amplifier.
Since the sensing circuitry on each side of the sub-array only accesses every other, or alternating, digit lines, the sense amplifiers may be implemented on the edge of the sub-array according to double the spacing, or pitch, of the digit lines. The physical space required to implement the sense amplifiers typically limits the density of the memory cells in the sub-array. Accordingly, the open digit line architecture with interleaved digit lines facilitates small digit line pitch sizes since the sense amplifiers are implemented on alternating sides of the memory sub-array. Furthermore, small digit line pitch sizes allow for high density sub-arrays which result in a large quantity of attached memory cells and a relatively large physical length of the digit line through the sub-array.
In order to prepare digit lines for sensing logic values from the memory cells, equilibrate circuits have been formed to electrically balance the digit lines. Conventional equilibrate circuits have been designed as part of the sense amplifier and have been designed according to larger feature sizes associated with the sense amplifiers. These larger feature sizes of the equilibrate circuit are undesirable in view of attempts to further reduce the size of a memory array and the associated circuitry.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved equilibrate circuit that does not affect the pitch of the interleaved digit lines.